OVERVIEW

The TrueSilicon PWM is a highly efficient configurable hardware block designed to generate periodic digital waveforms with programmable duty cycles while maintaining low power and area efficiency. It supports up to 16 independent channels, which can be configured either as unified or dedicated channels depending on system requirements. Each channel is built on a flexible 16-bit or 32-bit counter architecture, allowing precise control over frequency and duty cycle, with an additional programmable prescaler ranging from 1 to 2048 to further tune timing resolution.

The core provides advanced clocking flexibility by allowing each channel to operate on a separate clock source, with an optional clock divider that can be enabled or disabled. Additionally, timebases can be shared across channels using internal counter buses, enabling synchronized or coordinated waveform generation. The PWM supports both continuous mode for periodic signal generation and one-shot mode for single pulse applications. It also includes features such as synchronization and programmable phase shift between channels, which are particularly useful in motor control, power conversion, and multi-phase systems

To enhance output control, the PWM core includes support for complementary outputs with dead-band insertion, preventing shoot through conditions in power electronics. Each channel also offers output polarity control, allowing inversion of the generated waveform as needed

The PWM IP core generates interrupts on key events such as counter match, overflow, and period completion, enabling efficient interaction with the processor. It supports dynamic reconfiguration through an APB interface, allowing software to modify parameters like duty cycle, frequency, and mode on the fly

UTE_in is an external trigger input used to synchronize or control the operation of PWM channels and UTE_out is an output event signal generated by the PWM to trigger or synchronize other modules. The fully synchronous RTL design ensures clean clock-domain operation, predictable timing behaviour, and straightforward static timing analysis (STA).

The architecture is optimized for power, performance, andarea (PPA),making it suitable for a wide range of technology nodes and applications.Figure 1 depicts the high-level architecture of the TrueSilicon PWM IP, including the APB interface, showing generation of UTE_in and UTE_out along with pre scaler and programmable channels.